I\'ve implemented a 16-bit ALU and a register file in VHDL using the Xilinx ISE.I\'ve been asked how many slices my design uses, and I have no idea how to go about answering that question.I\'m not wor
I am using a Basys2 board to program a simple string detector to read patterns like \"0101\". I am using the Xilinix Design Suite 13.2 for this project. The.ucf file gives the following message.
I would like to initiate some BRAMs (I\'m using Xilinx FPGAs and ISE) with data from an image. It\'s bound to be thr开发者_StackOverflow中文版ough coe files but how? I could write a Java applet to man
I have been trying to fin开发者_Python百科d the Absolute value of an integer which is designated to Verilog core using Xilinx SystemC, what I have seen is that Verilog treats the negative number as a
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I have Xilinx ISE 13.1 installed on an ACER laptop with Win7 (64bit). After installing the software (WebPACK version) I created an empty VHDL module and ran \"check syntax\". The process failed with
When I do开发者_JAVA百科 some modifications in my code that runs on Microblaze, I sometimes see a large discrepancy in runtime for the execution of code that follows the same path. To illustrate, what
I just made a custom IP in Xilinx it generated a user_logic file which i required in Verilog, but i am having problems changing the code.
I was trying to generate a netlist from a simple Model in simulink. I can run the simulation开发者_运维百科 (usingsysgen).
I am trying to convert the input word coming out of the DQPSK Demodulator (Type : UFix2_0) to a serial stream.
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