How to determine how many slices a design uses

I've implemented a 16-bit ALU and a register file in VHDL using the Xilinx ISE. I've been asked how many slices my design uses, and I have no idea how to go about answering that question. I'm not working with a particular chip or simulating one, I just wrote the vhdl and debugged it by using a test bench.

Is there a way to get the ISE to generate how many slices my design uses? Or do I need to go through all my code and count up my operations? Or is it as simp开发者_JS百科le as defining what type of components I used?

To get a true view of what resources your design will consume use the map report. Implement the design and look at the hierarchical report of the usage (Slices, slice registers(or flip-flops), LUTS, LUTRAM, BRAM, DSPs, etc) of each module in your design in the map report file. In ISE 13.2 that is Section 13 of your _map.mrp file. You may have to enable the -detail switch in map.

Slices can be a deceptive metric (especially after a map report) since if you only use a single element of a slice it will count the entire slice as used. You will have to understand what is in a slice to really understand what the usage number means. Virtex 6 for example has 8 flip-flops and 4 6-input LUTS per slice.

If you only look at the synthesis numbers (slice flip-flops and slice LUTS) you may miss any netlist black boxes that your design uses (ie coregen elements, microblaze, system generator, or third party IP delivered in netlist form).

Ugh, I figured it out.

The trick is to click whatever module you want to get the slice count for and set it as the top level module by going to Source->Set as top level module. Once you do that, under the Processes pane (making sure the module is still highlighted in the Sources pane) go to the Synthesize - XST and double click 'View Synthesis Report'. The number of slices for that module is then listed in that report.