I\'ve implemented a 16-bit ALU and a register file in VHDL using the Xilinx ISE.I\'ve been asked how many slices my design uses, and I have no idea how to go about answering that question.I\'m not wor
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I am running Nexys2-1200 board (with a spartan3).It com开发者_StackOverflowes with a preloaded configuration that displays a VGA test pattern, that works fine.
I am working on awlan Receiver and using USRP2 for receieving the signal.I would like to know what should be the sampling rate that the Receiev开发者_Python百科er be operated on ?
I have added some functionalityin the FPGA code( Verilog) in USRP2. I would like to debug the code. Can you please suggest开发者_JS百科, how to debug the FPGA code .
I have been trying to fin开发者_Python百科d the Absolute value of an integer which is designated to Verilog core using Xilinx SystemC, what I have seen is that Verilog treats the negative number as a
I\'d like to approximate the ex function. Is it possible to do so using multiple splines type based approach? i.e between x1 and x2, then
Is there any TFTP Server for Altium Nanoboard NB3000 using the processor TSK3000A. The example from the Altium gives a webserver and it doesnt use any file system.
By Using cosmiac tutorial 13 http://www.cosmiac.org/tutorial_13.html and ISE 10.1 the pdf file shows how to generate an image and you can download the project by clicking the first .zip file. At the e
I am using USRP2 with RFX2400开发者_C百科 Daughterboard. I plan to use the USRP2 for my project.
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