Finding Absolute Value In Verilog Data Designated by System C/Xilinx X

I have been trying to fin开发者_Python百科d the Absolute value of an integer which is designated to Verilog core using Xilinx SystemC, what I have seen is that Verilog treats the negative number as a positive number.

I have tried all data types : signed int , int, Xuint32.

my SystemC or Xilinx C code is:

signed int data,value;
data=-20;value=0;
putfsl(data,0);
getfsl(value,0);
signed int data1,value1;
data=20;value=0;
putfsl(data1,0);
getfsl(value1,0);

After getting the values of variables I printed them on Hyperterminal.

On my Verilog side the code was:

out <=(in<0)?-in:in;

I also tried this code but results were similar

if(in<0)
out=-in;
else 
out=in;

Kindly help me out!

I have also tried other data types and changed parameters but results have not worked out to be I always get The same number I input i.e

in<0

statement is not being true, I also tried in<=0;

I can't help with System C, but based on your comments the Verilog code is using an unsigned type for the signal in.

reg [31:0] in;
if(in<0) //This will always be false since reg is unsigned
  out=-in;
else 
  out=in;

In order for this to work in would have to be declared as signed.

signed reg [31:0] in;

You can still test an unsigned value for a negative value(assuming in actually holds a two-complement value) by looking at the MSB.

//If negative
if(in[31])
  out = -in;
else
  out = in;

Well i Finally came to find out the answer really worked as suggested by some one.Thanks to Him (Martin Thompson)

The Answer is: Prior to Verilog-2001 all vector arithmetic in Verilog was unsigned.

In Verilog-2001 you can explicitly call for signed arithmetic, so I think you'll need to cast your in:

if ($signed(in) < 0)
 out = -$signed(in);
else
 out = in;

Reading matter which may be of interest:

Signed arithmetic in Verilog-2001 - Opportunities and Hazards