Considering this code: architecture synth of my_entity is signal a : std_logic; begin a <= c and d; b <= a an开发者_开发知识库d c;
I\'ve implemented a 16-bit ALU and a register file in VHDL using the Xilinx ISE.I\'ve been asked how many slices my design uses, and I have no idea how to go about answering that question.I\'m not wor
Data_Int<=\'0\' & Data_Int(7 downto 1); --if shift then shift it right How is concatenation used to shift a position? I thought there is a shift right operator in VHDL. Can someone please exp
What is the easiest or simplest way to check if an integer 开发者_如何转开发signal is even or odd in VHDL?if (A mod 2) = 0 then
I am running Nexys2-1200 board (with a spartan3).It com开发者_StackOverflowes with a preloaded configuration that displays a VGA test pattern, that works fine.
Hello I am trying to learn VHDL in xilinx ISE enviroment and I can not get this code to work and i do not know why. I have tried single quotes using/not using ands, but nothing works. Could someone pl
I would like to initiate some BRAMs (I\'m using Xilinx FPGAs and ISE) with data from an image. It\'s bound to be thr开发者_StackOverflow中文版ough coe files but how? I could write a Java applet to man
Suppose you have a loop for i in 1 downto 0 loop for j in 1 downto 0 loop tS0 <= i; But I need to convert the integer (which is natural) to std_logic. tS0 is declared as std_logic. I am only doi
I am loading text data into a VHDL test bench and I开发者_运维百科 want to convert input strings into integer values.
I need to make a vhdl parser. I decided to use the antlr parser generator and the vhdl grammar from their website http://www.antlr.org/grammar/1202750770887/vhdl.g.
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