How can I check if a VHDL Integer is even or odd?

What is the easiest or simplest way to check if an integer 开发者_如何转开发signal is even or odd in VHDL?

if (A mod 2) = 0 then
-- it's even
else
-- it's odd
end if;

As a side note if the signal is a vector, then you can do the following:

if (A(0)) then
-- it's odd
else
-- it's even

function is_even(val : integer) return boolean is
    constant vec: signed(31 downto 0) := to_signed(val, 32);
begin
   return vec(0) = '0';
end;

or

function is_even(val : integer) return boolean is
begin
   return val mod 2 = 0;
end;

depending on whether your synthesiser is bright enough to figure out mod 2

Another way if you are not storing as an integer * is to register the LSB from the standard logic vector holding the value and check if it is 0 or 1.

EDIT: Re-storing integers

removed * (which can be a problem on many FPGA's)

My mistake here, I was thinking along two different paths and mixed the two up. I have had trouble before passing character and string types between components when coding on FPGA's. While I cannot list the error messages off hand, I took a mental note to use std logic vectors instead of the pre-compile types. I found that they always seemed to work in simulation but never on the board.