I 开发者_如何学运维am having some trouble using the Slice block(Xilinx Bit Slice Extractor).
I am writing a开发者_运维知识库 code using VHDL to convert 24MHz and 12 MHz clock to 8 MHz clock. Can anyone please help me in this coding? Thanks in advance. Is this for an FPGA? Or something else? A
I am having some trouble understanding the concept of Timing Signals in Simulink (Xilink Library). I will explain with an example,
This must be the most common problem among people new to VHDL, but I don\'t see what I\'m doing wrong here! This seems to conform to all of the idioms that I\'ve seen on proper state machine design. I
I need to get the absolute of the signal in Xilinx Simulink. 开发者_如何学编程I can use a mcode block and write matlab code to achieve it. But, just curious if there is a better way of doing it.
I am working with Mentor FPGA doing RTL design with moduleware and vhdl.Right now I am looking at th开发者_如何转开发e Mentor Graphics Precision RTL synthesis GUI.Does anyone know how I can get a crit
I am implementing a DQPSK modulator and Demodulator. I would like to calculate the exp(1j*Phase) in Simulink.
I am trying to build a DBPSK demodulator using Simulink and Xilinx blockset. I calculate the Phase Difference of the Successive samples like this :
How does one for example make the best use of retiming and/or c-slow to make the most of a given pipeline.
I would like to know the proper procedure to cr开发者_C百科eate a PROM file (.MCS) for a serial SPI Flash that include BOTH the FPGA configuration bitstream and the software to be used by the Microbla