Critical Path from FPGA in Mentor

I am working with Mentor FPGA doing RTL design with moduleware and vhdl. Right now I am looking at th开发者_如何转开发e Mentor Graphics Precision RTL synthesis GUI. Does anyone know how I can get a critical path using this tool?

Synthesis is only vaguely aware of the possible physical layout of your design. It may know what's not physically possible and the boundaries of performance of the target architecture and primitives, but not a whole lot more. You will only get a meaningful critical path(s) after you've run the design through place and route and run the tool's timing analysis.