I am getting error as \"ERROR:Xst:827 - \"C:/1553/decoder_copy/decoder.vhd\" line 265: Signal no_words cannot be synthesized, bad synchronous description\".
I am writing a开发者_运维知识库 code using VHDL to convert 24MHz and 12 MHz clock to 8 MHz clock. Can anyone please help me in this coding? Thanks in advance. Is this for an FPGA? Or something else? A
Just wondering if I\'m implementing a finite state machine in VHDL whether or not I need to state what all of the outputs are in every possible state? Even if I know that some outputs won\'t change fr
I want to use tg68 core but there is a problem. When I compile my design in Altera Quartus it gives me 16 data_in and 16 data_out signals, and i need to join them into inout pins.
This must be the most common problem among people new to VHDL, but I don\'t see what I\'m doing wrong here! This seems to conform to all of the idioms that I\'ve seen on proper state machine design. I
I want a RAM in VHDL (that can synth开发者_开发问答esize on Xilinx, Altera..) with the following \'catch\' -
How does one for example make the best use of retiming and/or c-slow to make the most of a given pipeline.
I\'m creating a program counter that is supposed to use only unsigned numbers. I have 2 STD_LOGIC_VECTOR and a couple of STD_LOGIC. Is there anything I need to do so that they only use unsigned? At
I have big problem because i dont uderstand properly how make my homework. Well i have to make something like this:
We are looking at moving some code into a CPLD or FPGA in order to make it faster. I have worked with Xilinks and their suite of tools before, but for some reason it was decided that we\'d use Altera