Can anybody let me know what is the problem with the following vhdl code?

I am getting error as "ERROR:Xst:827 - "C:/1553/decoder_copy/decoder.vhd" line 265: Signal no_words cannot be synthesized, bad synchronous description".

     process(rst_n,dword_int,sy开发者_StackOverflow中文版nc_csw_reg,sync_dw_reg)
     begin
if(rst_n='1')then
    noofwords<="00000";
    no_words<="00000";
    nfw<='1';
elsif(falling_edge(sync_csw_reg) and dword_int(10)='0' and nfw='1' )then
    noofwords<=dword_int(0 to 4);
    check_nfw<=dword_int(0 to 4);
elsif(falling_edge(sync_dw_reg))then
    if(no_words = noofwords)then
        no_words<="00000";
        nfw<='1';
    else
        no_words<= no_words+'1';
        nfw<='0';
    end if;
end if;

end process;

I guess it's because you are checking for the edge of two different signals (sync_csw_reg and sync_dw_reg) in one process. You cannot do that if you want to synthesize the code. You have to separate it into two processes.