VHDL TG68 core data_in and data_out to datainout

I want to use tg68 core but there is a problem. When I compile my design in Altera Quartus it gives me 16 data_in and 16 data_out signals, and i need to join them into inout pins.

Here is some code I wrote in VHDL, and need someone who can check my code because I think that code is ok. This is code for top-level design file, which needs to generate inout pins from data_in and data_out signals from tg68.vhd file. Also it needs to have all signals from tg68.vhd usable in final design. (signals like as, uds, lds...)

Here is the code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity datainout is
    port(
    clk          : in std_logic;
    reset        : in std_logic;
        clkena_in    : in std_logic:='1';

        IPL          : in std_logic_vector(2 downto 0):="111";
        dtack        : in std_logic;
        addr          : out std_logic_vector(31 downto 0);

        as            : buffer std_logic;
        uds          : buffer std_logic;
        lds          : buffer std_logic;
        rw            : buffer std_logic;
        drive_data    : out std_logic;
        dataino开发者_如何学编程ut : inout std_logic_vector(15 downto 0)         
        );
end datainout;

ARCHITECTURE logic OF datainout IS

    COMPONENT TG68
    PORT (
      clk          : in std_logic;
    reset        : in std_logic;
        clkena_in    : in std_logic;
        data_in      : in std_logic_vector(15 downto 0);
        IPL          : in std_logic_vector(2 downto 0);
        dtack        : in std_logic;
        addr          : out std_logic_vector(31 downto 0);
        data_out      : out std_logic_vector(15 downto 0);
        as            : out std_logic;
        uds          : out std_logic;
        lds          : out std_logic;
        rw            : out std_logic;
        drive_data    : out std_logic
        );
    END COMPONENT;

signal data_in : STD_LOGIC_VECTOR (15 downto 0);
signal data_out : STD_LOGIC_VECTOR (15 downto 0);

BEGIN

data_in <= datainout;
TG68_inst: TG68
    PORT MAP (
        data_in => data_in,
    data_out => data_out,
    clk => clk,
    reset => reset,
    clkena_in => clkena_in,
    IPL => IPL,
    dtack => dtack,
    addr => addr,
    as => as,
    rw => rw,
    uds => uds,
    lds => lds,
        drive_data => drive_data   
        );

datainout(15 downto 8) <= data_out(15 downto 8) when as = '0' and rw = '0' and uds='0' else "ZZZZZZZZ";
datainout(7 downto 0) <= data_out(7 downto 0) when as = '0' and rw = '0' and lds='0' else "ZZZZZZZZ";
END;   

The basic way of doing inout signals is:

data_in   <= data_pins;
data_pins <= data_out when enable = '1' else (others => 'Z');

As far as I can see, this is exactly what you have done, but with the data bus split in two halves. Assuming that's what you intended, that's fine!