Where to force xilinx ISE to use block-rams?

I synthesized a small device to test the block-ram inference.

I got a message from XST :

The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_sty开发者_如何学Pythonle.

However, I don't know where to find this option/constraint either in ISE (11.1 in my case) or in constraint files...

I don't want to use VHDL attributes directly in my code.

In your project directory, you'll find a file called "your-design.xst". You can add the following at the end of the list (or anywhere after "run"):

-ram_style block # ( | auto | distributed )
-rom_style block # ( | auto | distributed )

These should make sure you're going to get BRAM mapping instead of distributed RAM (which means LUT-based memory).

This option could also come in handy:

-auto_bram_packing yes # ( | no )

Remember that each of those must be on a line of their own, and that you'll need to remove the "#" and whatever comes after that.

If you're using the ISE GUI, go to

Synthesis -> Process Properties -> HDL options

and choose the above options there.

(BTW, we're trying to start an SE site dedicated to FPGAs... consider supporting it... http://area51.stackexchange.com/proposals/20632/programmable-logic-and-fpga-design?referrer=YmxhQ2OJUo-FAaI1gMp5oQ2)

run -ram_style BLOCK can do the trick in command line.