Problem with net instantiation

I have a very simple statemachine that sets some control signals to interact with a third party IP. The code looks roughly as follows:

entity testip is
  port (
  ...
    fifo_dataout        : in  std_logic_vector(0 to 31);
    ip_dataout          : in  std_logic_vector(0 to 31);
    ip_ce                 : out std_logic;
    ip_we                : out std_logic;
    ip_datain            : out std_logic_vector(0 to 31);
  );
end entity testip;

architecture imp of testip is

  signal ip_ce_ns     : std_logic;
  signal ip_we_ns     : std_logic;
  signal ip_ce_cs     : std_logic;
  signal ip_we_cs     : std_logic;
  signal ip_dataout_i : std_logic_vector(0 to 31);
  ...

  attribute keep: string;
  attribute keep of ip_ce    : signal is "True";
  attribute keep of ip_we    : signal is "True";

  begin

  COMB : process (...)
      begin
        ip_ce_ns          <= ip_ce_cs;
        ip_we_ns          <= ip_we_cs;

     case ip_nstate_cs is
        when IDLE      =>
        ...

     end case;
 end process COMB;

 REG: process (Clk) is
   begin
      if (Clk'event and Clk = '1') then
         if (Rst = '1') then
              ip_ce_cs                <= '1';
              ip_we_cs                <= '1';
              ...
         else          
              ip_ce_cs                <= ip_ce_ns;
              ip_we_cs                <= ip_we_ns;
              ...
         end if;
    end if;
 end process REG;

S0:     ip_ce                 <= ip_ce_cs;
S1:     ip_we                <= ip_we_cs;
S2:     ip_datain           <= fifo_dataout;
S3:     ip_dataout_i       <= Ip_dataout;

end architecture imp;

Sythesis works fine, however, when applying the following constraint file I get ERROR:ConstraintSystem:59 - NET "testip/ip_we" not found. The same occurs for testip/ip_datain and testip/ip_ce.

 Net testip/ip_datain<*> MAXDELAY = 2 ns;
 Net testip/ip_ce MAXDELAY = 2 ns;
 Net testip/ip_we MAXDELAY = 2 ns;

I checked the netlist, and indeed there is neither a testip/ip_we, a testip/ip_ce nor a testip/i开发者_C百科p_datain net. Anyone an idea why the other nets are not in the netlist, all very confusing.

Many thanks for any feedback!

EDIT: Please see attached the detailed instantiation in the top module file:

icap0 : entity icap.hwicap
    generic map (pindex => 2, paddr => 2, pmask => 16#FFE#, C_SIMULATION => 2,
           C_FAMILY => "virtex5")
    port map (rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(2));


Net icap0/icap_statemachine_I1/Icap_datain<*> MAXDELAY = 2 ns;
Net icap0/icap_statemachine_I1/Icap_ce MAXDELAY = 2 ns;
Net icap0/icap_statemachine_I1/Icap_we MAXDELAY = 2 ns;

This should do the job, but when looking at the netlist and looking for signals Icap_ce or Icap_we they are just non-existent. I just think these nets are not there or have been renamed so that I cant find them anymore. Thanks

The signals were probably optimized away...it looks like you have a wire loop generating ip_ce and you're driving ip_datain with the non-existant fifo_dataout. You don't indicate what you're targeting, but modern FPGA synthesis are by default very aggressive at removing unused/undriven logic, typically with nothing more than an info or warning message in the log. Crawl through your syntheses logs and look for anything odd related to the signals you're looking for.

As Charles says, your signals are probably being optimized away.

If you set the synthesis attribute to preserve hierarchy, then your ports will be maintained (but you miss out on some optimizations).

I guess you aren't really as bothered about the signals as your are about the timing. In which case, use a start and end point, rather than a net name in your constraints.

Alternatively, you can set the keep attribute on the signals in the source code. That can of course make your source code less portable. My recommendation would be to use start and end points.

Is testip your top level? If not try

Net "*/testip/ip_ce" MAXDELAY = 2 ns;

is this net detected?

Net "*/testip/ip_ce_cs" MAXDELAY = 2 ns;

Actually, I've missed something more obvious, what is the name of the instance of testip? Use that instead of testip in your constraint. i.e.

u_test_ip : testip

then

Net "*/u_test_ip/ip_ce" MAXDELAY = 2 ns;

I think the keep attribute is case-sensitive, have you tried "true" rather than "True"?