How to reduce number of logic elements

I am trying to reduce the number of logic elements in my vhdl code. I am using quartus II to program a Altera DE2 FPGA开发者_如何学JAVA. Can someone please give some advice on how I can do that ?

Thanks

Without additional detail of your design, only generic advice can be given.

There are many ways to reduce device utilization in an FPGA, which break down into two major categories:

1. Better use of your build toolset (synthesis, map, p&r tools)
2. Better HDL design

Build Toolset Areas to Look For

• Set tool to optimize for area instead of speed
• Enable tool to allow resource sharing, retiming, and pipelining (as available and appropriate)
• Are your constraints being properly applied to your design? If not, the tools could be "working harder" in order to meet your constraints creating more logic/area utilization.

HDL Design Areas to Look For

• Consider your target device's architecture. Can you make use of device specific features to save on general logic? (examples: internal block memory for large LUTs, FIFOs, RAMs/ROMs, dedicated multipliers, etc)
• Use the tool output to determine areas to optimize in your HDL design. Look at your RTL and technology views. Analyze your critical paths. Are there places where trades could be made?
• Look at HDL coding guidelines published by Altera for their synthesis tools. Does your code implementation match recommendations made in documentation in order to gain best synthesis results?

If you have more specific concerns, please add an update.

Check out the relevant chapter of the Quartus II Handbook: Area and Timing Optimization (Vol 2, Ch 13)