X, Y, Z, T are different jobs. Ex, X = Multiplexer( ... )开发者_JAVA技巧 if ( empty1 ) if ( empty2 )
I\'m in the process of learning VHDL and I\'m trying just learning from examples, syntax guides, and experiments.
this question probably wont be explained very well and that\'s because I don\'t really understand what\'s happening in my design.
I have a very simple problem but I do not get my head around what is going wrong. Essentially, the whole thing works fine when simulating it, however, having it
I have this piece of IP that is supposed to be a 32 bits byte addressable memory. But I can\'t make it infer block rams, it is inferring a huge amount of flip flops...
I need to read a small image (tif format) from PC to FPGA kit (ALTERA DE2-70) for processi开发者_StackOverflow社区ng, then write it back to PC. I have no idea how to do it in Verilog?
I am designing universal shift arithmetic operator. Is there a better way to achieve it besides using the 32bit multiplexer (decoder) in a way presented bellow?
I am trying to re-use netlists in other designs without the success. I have a component which is translated to the netlist:
Similar to this post http://feedproxy.google.com/~r/cadence/community/blogs/fv/~3/IvdCIla8_Es/extending-multiple-when-subtypes-simultaneously.aspx
I wrote a counter in Verilog, and then a testbench to test it. My testbench gives the correct results, so my code is OK. But is it gives the result of a long time instantly.
加载中,请稍侯......