How is a variable shown in a RTL viewer in Quartus?

How is a variable depicted in a RTL viewer in Quartus. I open RTL viewer and it does not show any register for a variable.

For example:

variable op_code   : std_logic_vector(7开发者_运维问答 downto 0);

Is there a reason why RTL viewer will not show op_code in RTL viewer? I am using VHDL.

Edit:

op_code(7 downto 0) <=instr_reg(31 downto 24);

if ( op_code = ADD or op_code = MYSUB) then <br>
    C_addr <= instr_reg(14 downto 10); <br>
end if;             

CASE op_code(7 downto 0) IS
    --some case statments
END CASE;

Has it been optimised away? if the elements of opcode are used for other things, they may have been subsumed into other logic and not visible in their own right anymore.

Another thought - if you haven't described the behaviour of a register (which for a variable usually comes down to reading it before writing to it in a clocked process) then no register will be created. It'll just be combinatorial logic within the process, and very likely to be combined with other things. Maybe you could post your whole process (or a bit more of it) - we might be able to help more that way.