We are looking at moving some code into a CPLD or FPGA in order to make it faster. I have worked with Xilinks and their suite of tools before, but for some reason it was decided that we\'d use Altera
How is a variable depicted in a RTL viewer in Quartus. I open RTL viewer and it does not show any register for a variable.
I have never done this before and am very beginner in this one, so please treat me that way and help me. Obviously this is a complex topic for me at this stage.
加载中,请稍侯......