Datatype problem in simple IF statement in VHDL

I have a really weird开发者_如何学C problem and I am not 100% why the compiler is complaining. The code is as follows:

variable a : std_logic_vector(2 downto 0);
variable b : std_logic;
....
if (a = "100") AND (b) then
  -- do something
elsif (a = "011") OR (b) then
  -- do something else

I get the error message:

"AND can not have such operands in this context",
"OR can not have such operands in this context", respectively for the second IF statement.

Any idea why VHDL does not like this construction and if there is a workaround for that?

VHDL is strongly typed - in a test context it expects booleans. Try (b = '1').

You are trying to compare a vector with bit, one was it to change your code slightly to:

if (a = "100") then if (b) then -- do something end if elsif (a = "011") then if (b) then -- do something else end if; end if;