IA-32 | reordering issue in a multiprocessor environment

I want to perform an atomic 'and' operation on IA-32.

Please consider the following situation:

; processor 0
lea     edx, var
mov  ecx, mask
mov  eax, [edx]
lock and [edx], ecx

; processor 1
lea     edx, var
mov  eax, 0xff
xchg [edx], eax

I'm not sure if it's possible that the store to 'var' by processor 1 can or cannot occure between the load and the store to 'var' by processor 0. So, is this working or do I need to spin lock like 开发者_开发技巧this:

; processor 0
push ebx
lea  edx, var
mov  ecx, mask
@@loop:
mov  ebx, [edx]
mov  eax, ebx
and  eax, ecx
lock cmpxchg [edx], eax
cmp  eax, ebx
jne  @@loop
pop  ebx

Thanks for any answer. Best regards.

EDIT: In other words: I want to perform the conjunction in 'Processor 0' and need to fetch the initial value.

An xchg that references memory automatically locks the bus (or locks the cache when/if the data is already in the cache). See the Intel reference manual, §8.3.1. (Warning: I haven't looked hard recently, but Intel used to rearrange their web site, invalidating links fairly quickly. If so, Googling for something like "intel reference 3a" should turn it up).