What is negation (not) of a bit vector in VHDL

What does it mean to do a negation of a bit vector in VHDL? For example if I have 10100111 which is a bit vector called temp and I do something like temp := no开发者_运维知识库t temp what will my output be?

A bit-wise inversion.

In general in VHDL (LRM 7.2.1): "For the unary operation not defined on one-dimensional array types, the operation is performed on each element of the operand, and the result is an array with the same index range as the operand."

You can use "not" on vectors. Just run the program below with ModelSim or ISim and the inverted/negated bit vector will be printed in the console.

LIBRARY ieee;
USE ieee.numeric_bit.ALL;

entity test is
end entity test;

architecture beh of test is

    function vec_image(arg : bit_vector) return string is
        -- original author Mike Treseler (http://mysite.ncnetwork.net/reszotzl/)
        -- recursive function call turns ('1','0','1') into "101"
        -------------------------------------------------------------------------------
        constant arg_norm        : bit_vector(1 to arg'length) := arg;
        constant center          : natural := 2;     --  123
        variable bit_image       : string(1 to 3);   --  '0'
        variable just_the_number : character;
    begin
        if (arg'length > 0) then
            bit_image       := bit'image(arg_norm(1));   -- 3 chars: '0'
            just_the_number := bit_image(center);              -- 1 char    0
            return just_the_number                          -- first digit
            & vec_image(arg_norm(2 to arg_norm'length)); -- rest the same way
            else
            return ""; -- until "the rest" is nothing
        end if;
    end function vec_image;
begin

    demo:process is
        variable bitvec : bit_vector (7 downto 0) := "10100111";
    begin
        report vec_image(bitvec);
        report vec_image(not bitvec); -- not bit vector
        wait;
    end process demo;

end architecture beh;

If you really want to negate a vector, you need to use a vector which has certain properties defined for it. Specifically:

• some notion of numerical value (so you can't use bit_vector or std_logic_vector, which are just collections of bits)
• some notion of "sign"

From the ieee.numeric_std package, you should use the signed type for this:

use ieee.numeric_std.all;
...
variable a,b:signed(8 downto 0);
...
a := "000000001";
b := -a;