SRA can not have such operands?

I have coded an algorithm in VHDL but I have this message that I don't understand "sra/sla can not have such operands in this context.". Any help please?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.conv_std_logic_vector;

entity hsl2rgb is
    generic(
        constant hue : integer := 85;
        constant sat : integer := 127
    );
    port(
        lum    : in  std_logic_vector(7 downto 0);
        ored   : out std_logic_vector(5 downto 0);
        ogreen : out std_logic_vector(5 downto 0);
        oblue  : out std_logic_vector(5 downto 0)
    );
end entity;

architecture behavioral of hsl2rgb is
begin

    process(lum)
        variable v : integer;
        variable m : integer;
        variable sextant : integer;
        variable fract : integer;
        variable vsf : integer;
        variable mid1 : integer;
        variable mid2 : integer;
        variable lumx : integer;
    begin
        lumx := to_integer(unsigned(lum));
        if (lumx < 127) then
            v := (lumx * (256 + sat)) sra 8;
        else
            v := (((lumx + sat) sla 8) - lumx * sat) sla 8;
        end if;

        if (v <= 0) then
            ored <= (others => '0');
            ogreen <= (others => '0');
            oblue <= (others => '0');
        else
            m := (2 * lumx) - v;
            sextant := (hue * 6) sra 8;
            fract := (hue * 6) - (sextant sla 8);
            vsf := (fract * (v - m)) sra 8;
            mid1 := m + vsf;
            mid2 := v - vsf;

            case sextant is
                when 0 =>
                    ored <= conv_std_logic_vector(v, 6);
                    ogreen <= conv_std_logic_vector(mid1, 6);
                    oblue <= conv_std_logic_vector(m, 6);
                when 1 =>
                    ored <= conv_std_logic_vector(mid2, 6);
                    ogreen <= conv_std_logic_vector(v, 6);
                    oblue <= conv_std_logic_vector(m, 6);
                when 2 =>
                    ored <= conv_std_logic_vector(m, 6);
                    ogreen <= conv_std_logic_vector(v, 6);
                    oblue <= conv_std_logic_vector(mid1, 6);
                when 3 =>
                    ored <= conv_std_logic_vector(m, 6);
                    ogreen <= conv_std_logic_vector(mid2, 6);
                    开发者_JAVA百科oblue <= conv_std_logic_vector(v, 6);
                when 4 =>
                    ored <= conv_std_logic_vector(mid1, 6);
                    ogreen <= conv_std_logic_vector(m, 6);
                    oblue <= conv_std_logic_vector(v, 6);
                when 5 =>
                    ored <= conv_std_logic_vector(v, 6);
                    ogreen <= conv_std_logic_vector(m, 6);
                    oblue <= conv_std_logic_vector(mid2, 6);
                when others =>
                    ored <= (others => '0');
                    ogreen <= (others => '0');
                    oblue <= (others => '0');
            end case;
        end if;
    end process;
end architecture;

With integers you'll have to use * and / operators. If they have constant powers-of-2 in the right places (ie on the right of the divide, either side of the multiply), the synthesiser will "do the right thing".

Or (as Charles noted) use signed or unsigned types from the ieee.numeric_std library.

BTW, why are you using conv_std_logic_vector when you have used ieee.numeric_std?

ored <= std_logic_vector(to_unsigned(mid1, 6));

should be what you require, then you can get rid of the nasty ieee.std_logic_arith library

(Aside: If you (or a future reader of this) are targeting an FPGA (and I accept you may not be but lots of people are these days:) you may find there is a need to pipeline that architecture somewhat if the target frequency is at all challenging. At a brief eyeball-synthesis, there are upwards of a half-dozen adders, a couple of real multipliers and a few muxes - all in a single clock-cycle. In particular this will preclude the use of the hard multipliers in all FPGAs I know of)

The problem is you have converted your std_logic_vector I/O into integers to perform math, but the sra/srl operands only work on 1D arrays of bit or boolean types. You will probably have much better luck trying to work with signed or unsigned types (which are bit-vector representations of numbers) instead of mixing std_logic_vectors (which have no inherent numeric value) and integers (which have no bit-vector representation).