How to manage reset signal for VHDL test benches?

I have a very simple vhdl testbench that should run. My components all have a reset signal, so that registers are set to 0 and other components correctly initialized... but... if I create a common sign开发者_JS百科al for resetting all component only during the first clock cycle, how can I tell to that signal to go down after the first clock cycle and never get up again????

I know it is a stupid problem but, how would you do???????? Thank you.

reset <= '1', '0' after 10 ns;