Making a 4-bit ALU from several 1-bit ALUs

I'm trying to combine several 1 bit ALUs into a 4 bit ALU. I am confused about how to actually do this in VHDL. Here is the code for the 1bit ALU that I am using:

component alu1 -- define the 1 bit alu component
  port(a, b: std_logic_vector(1 downto 0);
  m: in std_logic_vector(1 downto 0);
  result: out std_logic_vector(1 downto 0));
end alu1;

architecture behv1 of alu1 is
begin
  process(a, b, m)
  begin
   case m is
     when "00" =>
        result <= a + b;
      when "01" =>开发者_运维技巧
        result <= a + (not b) + 1;
      when "10" =>
        result <= a and b;
      when "11" =>
        result <= a or b;
    end case
  end process
end behv1

I am assuming I define alu1 as a component of the larger entity alu4, but how can I tie them together?

Interesting you would even ask that question. VHDL synthesizers are quite capable of inferring any adder you like. You can just type what you need:

use ieee.numeric_std.all;
...
signal r : unsigned(3 downto 0);
signal a : unsigned(2 downto 0);
signal b : unsigned(2 downto 0);
signal c : unsigned(2 downto 0);
...
r  <=  a + b + c;

Then you can slice r to fit your needs:

result  <=  std_logic_vector(r(2 downto 0));

You can't (easily) string together these 1-bit ALUs into a functional multiple bit version. There is no way to handle the carry in/out needed for your add and subtract modes to work properly (the bitwise and & or should work OK, however).

Ignoring the carry issue for the moment, you would typically just setup a for generate loop and instantiate multiple copies of your bitwise logic, possibly special casing the first and/or last elements, ie:

MyLabel : for bitindex in 0 to 3 generate
begin
  alu_x4 : entity work.alu1
  port map (
    a => input_a(bitindex),
    b => input_b(bitindex),
    m => mode,
    result => result_x4(bitindex) );
end generate;