Simulation not working - port mapping wrong?

VHDL code

First of all, sorry for the redirect, but it's easier that way. I'm building a digital clock, but as you can see, clock_AN and clock_seg_out do not change. Is this caused b开发者_开发知识库y a wrong port mapping? Thanks!

Your input master clock is too slow. Looking at the frequency divider cct, it looks like you've it programmed to divide a 100MHz clock. So either:

• speed up your testbench master clock
• or set the divider target to a lower number for debug purposes

Go with #2 if you want reasonable sim times!