Does Verilog support short circuit evaluation?

If I have an if statement like:

if(risingEdge && cnt == 3'b111)
begin
  ...
end

Will it check on cnt if risingEdge is not true?

Does this even matter inside of an HDL?

For simulation it is undefined as to whether short-circuited expressions are evaluated or not. In the above example it makes no difference, but if you have a function call on the right hand side then you may run into problems with undefined side effects.

See Gotcha #52 in "Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them" by Stuart Sutherland and Don Mills.

In terms of whether it matters in an HDL, I presume you are asking whether it would matter when synthesized. Short answer is that it would. For example, the following code is synthesizable SystemVerilog :

if(risingEdge && cnt++ == 3'b111)
begin
  ...
end

In Verilog (not SV) the post-increment could be replaced with a verilog function that has other assignments to module variables to show the same thing. So yes it is a relevant question.

Paul R is generally correct, and the Sutherland reference is a great one (lots of good things like that described in those Gotchas). For reference though, this has changed with SystemVerilog, at least as far as the specification is concerned. While Verilog specifies that short-circuited operations may or may not be executed, SV disambiguates this by indicating that implementations shall not evaluate the short circuited operands (similar to C++, Java, etc). See IEEE-1800-2009 section 11.3.5 if you are interested. While this is great, the track record for adhering to the SV spec is not stellar across all tool providers, so use care when relying on it in SV.