Case statements in VHDL

When programming in VHDL, can you use a variable in a case statement? This variable will modified by one of the cases

i.e.

case ta开发者_如何转开发sk is

when 1 =>

when 2 => 

when number =>

is this OK?

For simulation or synthesis?

Either way, from the documentation:

The choices must be constants of the same discrete type as the expression.

Use if to test for number, either:

if task=number then
  ...
else
  case task is
    when 1 => ...
    when 2 => ...
    when others => ...
  end case;
end if;

or

case task is
  when 1 => ...
  when 2 => ...
  when others =>
    if task=number then
      ...
    else
      ...
    end if;
end case;

Your choice depends on whether you want the result of the if task=number test or of the when ... => test to have priority? (e.g. assume that for whatever reason number=1, do you want when 1 => or if task=number to ultimately provide your result?)

In the trivial case the case statement synthesizes as a multiplexer; the if statement synthesizes as a comparator and two-input multiplexer. One feeds into the other.