Hardware representation for arrays in VHDL

Using VHDL i want to have a some registers that store 16 bit in each开发者_Python百科 one. So i found that VHDL have a built in array,and i want to use it to store 16 bit in each element in iy so i want to know if VHDL map this array to actual registers or not?

The short answer is no - the array type does not map to a register.

The long answer:

The array type in VHDL is just an indexed collection of elements of the same type. In your case, you'd probably use an array as the output from a register bank.

So, say you have a bank of 8 registers each holding 16 bits. The output from this bank would be an array (of size 8) of 16-bit vectors. The component declaration for this register bank would look something like this:

 component reg8x16
  port(
   clock: in std_logic;
   reset: in std_logic;
   enable: in std_logic;
   rout : out r_array(0 to 7)
   );
 end component; 

rout is your array of registered outputs from the register bank. So you can dereference the output of register 0 from the bank using rout(0), which is of type std_logic_vector(15 downto 0).

Also, don't forget to declare the array type somewhere (usually in a package file). It would look something like:

type r_array is array (integer range <>) of std_logic_vector(15 downto 0);

The (integer range <>) statement is a kind of placeholder for the array index range - it will be filled in later when the array type is used (such as in our component declaration above).

I'm not sure if this answers your question or not. I won't go into the specifics of how to create the reg8x16 component. Basically, you just create a 16-bit register whose output is of type std_logic_vector(15 downto 0); (you can look up how to do this online...it's pretty basic VHDL). Then you just instantiate 8 of those registers, and put them in the component named reg8x16.

An array is just like any other variable or signal: If you describe a behaviour which means it must remember its state from one clock tick to another, then flipflops (or memory blocks, if the conditions are right) will be inferred by the synthesiser.

Any array with a valid range would map to wires in generated netlist. This is fairly obvious- hardware contains only gates and wires. Something like a(3 downto 0)(1 to 0) would make to a 4x2 or 8-bit size wire. You now map individual accesses like a(3)(1) to indices in this 1-dimensional array. So a(3)(1) is basically a(7).

check this page, also check the register vhdl

basically it is an array of std_logic_vector with the required lengths