How to synthesis verilog cores made in xilinx core generator?

I used coregen to develop a divider core. Here are the steps I tried to use that div开发者_如何学运维ider in my design (not sure if its quite correct): 1) copied wrapper (core_name.v), .ngc file, and .veo file into main design folder 2) instantiate the core in my main verilog module using the veo template: core_name u1(.a(a_p), .b(b_p), .c(c_p), .d(d_p); whenever I need the divide function in my main verilog module 3) `include "core_name.v"

When I do a syntax check I get: "core_name.v" line 1 expecting 'endmodule', found 'module'

Please advise on the steps needed to instantiate the core in my ISE design and synthesize it.

Thank you.

I'm going to assume that core_name.v is a full module definition, and that you've put the ``include "core_name.v"within another module definition (ie, betweenmoduleandendmodulestatements. (I'm thinking this because the verilog parser will want to see anendmodulesometime after amodule, but instead is seeing anothermoduleincore_name.v`).

Try putting the ``include` outside your module definition, eg

`include "core_name.v"
module toplevel_module ( );

  core_name U0 ( .. );
endmodule

instead of what I assume you have:

module toplevel_module ( );
`include "core_name.v"
  core_name U0 ( .. );
endmodule