necessity of 'event

I have used below statement, frequently. However, I wonder

  if ( clock'event and clock = '1' ) then 
             [do something]

we really need to write clock'event in above statement ? If 开发者_JS百科yes, why?

You could get the simulation to work perfectly without the clock'event condition, but the synthesis will come out wrong.

The IEEE standard on synthesizable VHDL requires that you add clock'event. It is commonly accepted good practice to write if rising_edge(clock) instead. This conveys your intention a lot better. Both rising_edge and falling_edge functions are allowed as synthesizable VHDL constructs.

For simulation:

process (clock) is
-- stuff
begin
if clock='1' then -- EVIL! don't do this
  -- do things
end if;
end process;

Assuming that clock just switches from '0' to '1' and back (no meta-values), the behavior would be identical to what you'd get with a clock'event condition. Again, this will not synthesize to what you want! You'll probably get a latch, not a D flip-flop.

(Bonus points for whomever tries to synthesize this and gets back with the results!)

Yes, otherwise the following code executes the entire time your clock signal is high, not just at the rising edge of the clock.