Parameterized Bit-fields in verilog

Is it possible to parameterize a bit-field in verilog? Essentially I want to use a parameter or alternative to define a bit-range. The only way I can think of doing this is with a 开发者_运维技巧`define as shown below but it seems like there should be a better way.

`define BITFIELD_SELECT 31:28
foo = bar[BITFIELD_SELECT]

Parameters are nicer(safer) than defines since the namespace is not global to the project. You should be able to do this with two parameters.

parameter BITFIELD_HIGH = 31;
parameter BITFIELD_LOW = 28;

assign foo = bar[BITFIELD_HIGH:BITFIELD_LOW];

Alternatively

parameter BITFIELD_HIGH = 31;
localparam BITFIELD_LOW = BITFIELD_HIGH-3;

assign foo = bar[BITFIELD_HIGH:BITFIELD_LOW];

If you use macros (define) include the "`" when call the macro

`define BITFIELD_SELECT 31:28
foo = bar[`BITFIELD_SELECT]; // `BITFIELD_SELECT