"Warning C0007 : Architecture has unbound instances" issue!

I have the following source code from the CD attached with "Fundamental of Digital Design" book.

When I tried run the program, it gave me the following error:

Compiling Fig17_13.vhd...
C:\Users\SPIDER\Desktop\EE460\The Final Project\Fig17_13.vhd(25): Warning C0007 : Architecture has unbound instances (ex. ct2)
Done

How can I fix this issue?

Here is the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity c74163test is
    port(ClrN,LdN,P,T1,Clk: in std_logic;
       Din1, Din2: in std_logic_vector(3 downto 0);
       Count: out integer range 0 to 255;
       Carry2: out std_logic);
end c7416开发者_开发知识库3test;

architecture tester of c74163test is
    component c74163
       port(LdN, ClrN, P, T, Clk : in std_logic;  
         D: in std_logic_vector(3 downto 0);
       Cout: out std_logic; Qout: out std_logic_vector(3 downto 0) );
    end component;
    signal Carry1: std_logic;
    signal Qout1, Qout2: std_logic_vector(3 downto 0);
begin
    ct1: c74163 port map (LdN,ClrN,P,T1,Clk,Din1,Carry1, Qout1);
    ct2: c74163 port map (LdN,ClrN,P,Carry1,Clk,Din2,Carry2,Qout2);
    Count <= Conv_integer(Qout2 & Qout1);
end tester;

Did you actually read the instantiated design before (I guess it's in Fig17_12.vhd)? Otherwise your instance is just a blackbox (what I guess is meant by "unbound instance").

Think of a VHDL component as being like a plastic chip socket. Think of an entity as being like the chip that plugs into it. The instances in your code are of the components: think of your code as being like a PCB (your architecture) with some plastic sockets soldered to it (the components). You need the chips (the entities).

How do the chips find there way into the sockets? Or, in more formal terms, how do the entities get bound to the components. Well, (i) if their names are the same then binding happens automatically (but elaboration will fail if the ports are different). If the names are not the same (or if the ports are different), then you need to write a VHDL configuration to match up the entity to the component.

So, in your case, you either

(i) have not compiled the entity c74163 or

(ii) have done so, but the entity c74163 is not identical to the component c74163, ie:

entity c74163
   port(LdN, ClrN, P, T, Clk : in std_logic;  
     D: in std_logic_vector(3 downto 0);
   Cout: out std_logic; Qout: out std_logic_vector(3 downto 0) );
end entity;

You should ask yourself whether you really need to use component instantiation. Component instantiation was the only kind of instantiation before VHDL-93, but since then, you have the choice of also using direct instantiation, where you just instantiate the entities and don't use components at all. Think of direct instantiation as being like soldering chips directly to the PCB; no plastic sockets are involved.

Direct instantiation is usually the right choice: it's easier and you don't have to go to all the bother of having to write everything twice (in the entity and the component). The downside is that you now have to ensure that an entity is compiled before any architecture that instantiates it.

Here is your code written using direct instantiation:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity c74163test is
    port(ClrN,LdN,P,T1,Clk: in std_logic;
       Din1, Din2: in std_logic_vector(3 downto 0);
       Count: out integer range 0 to 255;
       Carry2: out std_logic);
end c74163test;

architecture tester of c74163test is
    signal Carry1: std_logic;
    signal Qout1, Qout2: std_logic_vector(3 downto 0);
begin
    ct1: entity work.c74163 port map (LdN,ClrN,P,T1,Clk,Din1,Carry1, Qout1);
    ct2: entity work.c74163 port map (LdN,ClrN,P,Carry1,Clk,Din2,Carry2,Qout2);
    Count <= Conv_integer(Qout2 & Qout1);
end tester;