What I'm doing

I started playing around with Xilinx ISE Design Suite and wrote simple Arithm开发者_运维知识库etical Logic Units in verilog. Using verilog Unit Under Tests to create input and output signals for ISim, I verified, that the code works just as I want it.

I would like to generate schematic file from the verilog source.

Under tools menu, there is a schematic viewer

, but I can not figure out, why:

• it only lists first source file
• and how to save generated file in project

Question:

How to generate schematic file from verilog source in Xilinx?

1) You can double-click on a component to go deeper. In newer versions of ISE that expands the block in-place instead of switching your view to the module clicked.

2) Apparently, there's no saving option. The schematics is generated from HDL code, so there's not much sense in saving it anyway.