? time delay, when using === or <=

When we use

input reg [7:0] ast, f_out;

ast === f_out ;

ast <= ast + 8'b00000001;

for those opera开发者_如何转开发tions " === and <= ", Have any time delay been occurred ?

EDIT: I think something small like 1 unit time, am I wrong ?

used language : verilog

There will be a simulation cycle delay if you use <= - ie a nonblocking assignment. Read up on blocking vs nonblocking assignments.

Also, === is not an assignment - its an equality operator that doesn't treat x and z as don't cares

Time delays are most commonly specified using #. Since I see no # in your code, there is probably no delay.

Another way to add delays is to use a specify block, and you don't show that either. There are plenty of examples of specify in the Verilog IEEE Std.

You can check for delays yourself by running a simulation and printing time values:

$display($time);