VHDL group multiple std_logic_vectors output into a single std_logic_vector

I have to design a 32-bit ALU by aggregating 8 4-bit ALU's I've already designed. What I can't figure out is how to take the 8 4-bit signals and link them to the 32-bit signals for the 32-bit ALU.

I want to say something like this (for the lowest 4-bit ALU):

  a0: four_bit_ALU port map(A      => A(3 downto 0), 
                            B      => B(3 downto 0), 
                            Cin    => sub, 
                            Less   => l, 
                            Cout   => c(0), 
                            Result => result(3 downto 0), 
                            OP     => m);

Where 'A' and 'B' are the two arguments to th开发者_如何学Pythone ALU and 'result' is the 32-bit output. Testing this gives all the result bits as undefined though. I have tested the 4-bit ALU and have no such problems.

Guess: Did you perhaps make a goof on the inputs to your 4-bit ALU, and leave something like Cin tied to an undefined signal?

You'll have to post more code if you expect any help other than slightly educated guesses.