Is there a VHDL equivalent to Verilog's @(*), i.e., automatic process sensitivity list

It is easy to update a combinatorial process and forget to update the sensitivity list. In Verilog the @(*) was introduced to say the sensit开发者_运维问答ivity list is what is used in this process. Is there an equivalent in VHDL?

I found this thread in comp.lang.vhdl. Sounds like VHDL-2008 adds wildcard sensitivity with process(all), but tool support varies.

If you can not use VHDL-2008 yet, Sigasi HDT can automatically insert the correct sensitivity list for you.

Emacs VHDL-mode can update them too. That's what I will go with.