How to do a VHDL "typedef"

I want to "create" a type "my_type", which is a开发者_如何学Python std_logic_vector(...), like this C/VHDL fake code: typedef std_logic_vector(CONSTANT downto 0) my_type.

"type" does not allow you to do it with std_logic_vector(...), only with array, and "alias" uses only valid types, you can't create a type with it.

So how to do it?

You need subtype

subtype foo is std_logic_vector(7 downto 0);