Xilinx ISE "Cannot access memory Q directly"

What is this error and what am I supposed to look f开发者_如何学Pythonor?

I got this error when I had done:

wire Q[3:0] when I should have had wire [3:0] Q;

It's also common under Xilinx Vivado that errors come up if you've imported SystemVerilog code and haven't set the source code type in the system navigator as such. Vivado defaults to making everything basic Verilog, and although pretty much everything in Verilog will synthesize fine if the file type is SystemVerilog, the reverse is not true.