Problem in using shell for loop inside gnu make?

consider the below make file

all: 
     @for x in y z; \ 
     do \ 
          for a in b c; \
          do \
                   echo $$x$$a >> log_$$x; \
          done; \
     done

While executing this make file, two file got created log_y and log_z. log_y is having data "yb" and "yc". similarly log_z is having data"zb" and "zc".

Actually I want to create four files(log_y_b, log_y_c, log_z_b, log_z_c). For this i have modified the above make file as,

开发者_开发百科
all:
     @for x in y z; \ 
     do \ 
          for a in b c; \
          do \
                   echo $$x$$a >> log_$$x_$$a; \
          done; \
     done

But its creating only one file log_. What should i have to do to create four files.

Perhaps put braces around the variable names: it works on my system.

all:
    @for x in y z; \
    do \
        for a in b c; \
        do \
            echo $$x$$a >> log_$${x}_$${a}; \
        done; \
    done

You can also use foreach:

all:
    @$(foreach x,y z,$(foreach a,b c,echo $(x)$(a) >> log_$(x)_$(a);))

log_$$x_$$a in the Makefile turns into log_$x_$a for the shell which is equivalent to log_${x_}${a}. The variable $x_ is undefined, however, so the shell substitutes it by the empty string.

Solution: Properly write the $x variable with curly braces around the name (${variablename}), i.e. for consistency's sake write log_${x}_${a} (or in Makefile style: log_$${x}_$${a}).