How to conditionally include a file into Makefile?

Consider the following Makefile:

# <include global configuration Makefile>

INCL = -I../include \
       -I<whatever>

CPPFLAGS=$(DEFS) $(INCL)
CXXFLAGS = -O0开发者_开发问答 -g -Wall -fmessage-length=0

SRCS = $(wildcard *.cpp)

OBJS = $(SRCS:.cpp=.o)

all: $(OBJS)

%.o: %.cpp
    $(CXX) $(CPPFLAGS) $(CXXFLAGS) -c -o $@ $<


depend: .depend

.depend: $(SRCS) 
    $(CPP) $(CPPFLAGS) -M $^ > $@

clean:
    rm -f $(OBJS)
    rm .depend


-include .depend

This Makefile creates an #include dependency chain using the g++ -M command, and includes it. This can be a rather long process. The problem is that this file is generated even if make clean is called, when this file would be deleted anyway. Is ther a way to conditionally include this file, and not bother creating it if the clean target is run?

Something like this:

ifneq ($(MAKECMDGOALS),clean)
-include .depend
endif

See the make manual page on Goals for more information

Edit: -include cannot be tab indented, otherwise it is ignored.

You can do such dependencies for free (i.e., at no runtime cost) during the compile. When you run clean, the dependencies are naturally not remade. See the section Combining Compilation and Dependency Generation in Paul Smith's Advanced Auto-Dependency Generation paper.