Simple MakeFile Problem

I made some changes to the Assembler (included new instructions that are also supported by the underlying hardware) which I wanna use in the code_asm files. The problem is, that the Makefile that I have at the moment uses the C Compiler to also compile the code_asm files. What I wanna do is to make sure that the file code_asm1 and code_asm2 are run through the modified assembler before the resulting object files are linked with the rest of the application. I tried some things but I am not succeeding hence it would be great if someone with some Makefile experience could quickly help me out开发者_如何学Python.

CC  = /mycom/bin/sparc-elf-gcc
AS  = /myass/bin/sparc-elf-as

CFLAGS  = -O2 -Wall -g

APP = test_V3

COBJ    = file1.o \
          file2.o \
          file3.o

ASMOBJ_V3 = code_asm1.o \
              code_asm2.o   

all: $(APP)

# produce application

test_V3: $(ASMOBJ_V3) $(COBJ) Makefile
    $(CC) $(EXTRAFLAGS) -o $@ $(COBJ) $(ASMOBJ_V3)  

Thanks a lot, Chris

You need to specify dependencies for your assembler sources, e.g.

code_asm1.o: code_asm1.asm
    $(AS) -o $@ $<

(assuming your assembler sources have a .asm suffix of course - change it appropriately if it's e.g. .S)

You need to overwrite the standard rule to create .o files:

%.o : %.c
    $(CC)   $(CFLAGS)  -o $@ $<

Just define your own rule to build asm.o files based on asm.c files to replace the above standard rule.