How does $@ work in a make conditional?

I'm using GNU Make 3.80. In my Makefile, I use automatic variable $@ to refer to the current target.

    @echo current target is ... [$@]
ifeq ($@,sms)
    @echo yep, they are equal
else
 开发者_运维问答   @echo no, they are not equal
endif

It seems that $@ expands to sms, as shown in the output below.

Output is:

current target is ... [sms]
no, they are not equal

My question: since $@ (apparently) expands to sms, shouldn't the "true" branch of the ifeq conditional be executed (with the consequence that the output should read yep, they are equal)? [I am at a loss as to why the output is no, they are not equal.]

From the GNU Make manual:

10.5.3 Automatic Variables ... It's very important that you recognize the limited scope in which automatic variable values are available: they only have values within the recipe. ... there is a special feature of GNU make, secondary expansion (see Secondary Expansion), which will allow automatic variable values to be used in prerequisite lists.

That is, $@ can only be used inside the section containing commands to build the target and, with some restrictions, inside the prerequisites list.

However you can use shell commands to implement conditions inside the list of commands used to build the target:

    @echo current target is ... [$@]
    if [[ "$@" == "sms" ]]; then \
         echo yep, they are equal; \
    else \
         echo no, they are not equal; \
    fi

Also if you want to check what targets were specified on the command line use MAKECMDGOALS variable.