Dependencies in Makefiles

Suppose I have a Makefile:

all: $(BINARY)

$(BINARY): $(OBJS) $(DEBUG_OBJS)
    #Link objects here

$(OBJS): headers
    #Compile code into objects without debug option

$(DEBUG_OBJS): headers
    #Compile code into objects with debug option

开发者_Go百科headers:
    #Create on-the-fly header files

As you can see, the target headers is required by both $(OBJS) and $(DEBUG_OBJS). The question is, will headers be called twice? Also, would the below code be equal/equivalent to the above:

all: $(BINARY)

$(BINARY): headers $(OBJS) $(DEBUG_OBJS)
    #Link objects here

$(OBJS): 
    #Compile code into objects without debug option

$(DEBUG_OBJS): 
    #Compile code into objects with debug option

headers:
    #Create on-the-fly header files

in that, would headers get called before $(OBJS) and $(DEBUG_OBJS) by $(BINARY)?

No, headers will be done just once.

You can write a simple makefile to test it:

all: foo bar

foo: baz

bar: baz

baz:
        echo 'hi'

On doing make, hi will be echoed just once.

And in your 2nd case make sees that $(BINARY) depends on headers first, so it goes and does headers before other dependencies.