How to wire two modules in Verilog?

I have written two modules DLatch and RSLatch and i want to write verilog cod开发者_JAVA技巧e to join those two.

Seriously, you should get yourself a Verilog handbook or search for some online resources.

Anyway, something like this should work:

module dff (
    input Clk,
    input D,
    output Q,
    output Qbar
  );

  wire q_to_s;
  wire qbar_to_r;
  wire clk_bar;

  assign clk_bar = ~Clk;

  D_latch dlatch (
    .D(D),
    .Clk(Clk),
    .Q(q_to_s),
    .Qbar(qbar_to_r)
  );

  RS_latch rslatch (
    .S(q_to_s),
    .R(qbar_to_r),
    .Clk(clk_bar),
    .Qa(Q),
    .Qb(Qbar)
  );

endmodule

You might want to look into Emacs AUTOWIRE

You will need to create an outer module, with the ports as shown in your schematic (D, Clk, Q, NQ). Inside this module you instantiate the two submodules DLatch and RSLatch, and wire the ports appropriately. (You will need to declare extra wires for the internal interconnects.)