Can't make sense of error in System Verilog

I tried to compile code

module counter(
    input clk,
    input upSignal,
    input downSignal,
    output [7:0] count
   );
        always_ff @(posedge clk) begin
          if 开发者_高级运维(upSignal)
              count <= count + 1;
          else if (downSignal)
              count <= count - 1;
        end
    endmodule

but I get the error

Error (10170): Verilog HDL syntax error at counter.v(7) near text "@"; expecting ".", or "("

what does it mean?

Quartus does support some systemverilog. See this link for details > Quartus Help

For quartus to automatically recognise that you are using system verilog, you need to call your file something.sv

So in this case, probably counter.sv

If your file is called counter.v, then you will get an error. I can confirm that is does indeed compile with Quartus II v10.0.

I would recommend changing your module output port to reg, Quartus didn't complain, but a simulator would.

output reg [7:0] count

Let us know how you get on.

Cheers

I think George is right (Hello George! Fancy seeing you here), the file is being interpreted as Verilog (not SystemVerilog), and so it doesn't understand always_ff.

On the type of the output value, I prefer the use of logic in SystemVerilog. Its effect is identical, but it gets away from the "Its declared 'reg' therefore it's a register' thinking that can catch people out.

Also, the reason you got that particular error message was that because it didn't know what always_ff was, it assumed it was the name of a module/interface/function. A module could have a port map that could start with a '.', and everything else would need an open bracket.

One other problem with this code.

The count variable is assigned from a procedural block (always_ff) so the count variable needs to be declared as a variable type, typically logic type for this SystemVerilog code. The declaration should include: output logic [7:0] count