Compiling with different flags in Makefile?

I have a single program used to interact with a joystick. It uses conditional compilation to specify a specific joystick. We do this right now by just hard coding the correct flag into the Makefile.

I'd like to make it so it uses a d开发者_运维百科ifferent flag based on the command given to the Makefile. So for example, I currently have this:

.PHONY: saitek
saitek: $(SOURCES)
    $(COMPILE) -DSAITEK
.PHONY: logitech
logitech: $(SOURCES)
    $(COMPILE) -DLOGITECH

I want only one of these commands to ever be run, and I want them all to make the same executable. But if I rerun 'make' it will compile the program again. I'd like it to recognize that it's already built the program.

Is there anyway to do this with a Makefile?

If you're using GNUMake, this will do what you're asking. It uses a different flag based on the command given to Make, and it doesn't rebuild the program unnecessarily.

.PHONY: saitek logitech
saitek: JOYSTICK=SAITEK
logitech: JOYSTICK=LOGITECH

# Suppose the actual name of your executable is "program"

saitek logitech: program

program: $(SOURCES)
    $(COMPILE) -D$(JOYSTICK)

GNU make inherits variables from its environment, so if you specify

$ JOYSICK=LOGITECH

in your shell, and use

CFLAGS+=-D$(JOYSTICK)

in your makefile.

I question the necessity of this. You could just call make as something like make CFLAGS=-DSAITEK or use autoconf and substitute in the correct defines.

That said, how about something like this:

saitek logitech: program
.PHONY: saitek logitech

ifeq ($(MAKECMDGOALS),saitek)
CFLAGS += -DSAITEK
endif
ifeq ($(MAKECMDGOALS),logitech)
CFLAGS += -DLOGITECH
endif

program: $(OBJS)
# Whatever