Implicit Rules in Makefile

hi i want to do a Makefi开发者_如何学编程le in linux that will take all the .cpp files in the dir compile them and create one .o file that i can active how i can do it with Implicit Rules

thanks mati

Implicit rules will help you create the object files, but combining them together will have to be done explicitly (as it is something that is rarely done).

OBJ = a.o b.o

big.o : ${OBJ}
    ${LD} -r -o $@ $^

Or maybe you can try following method after properly defined the variables:

.o: .cpp
    $(CPP) -c $(CPPFLAGS) $< -o $@
$(EXECUTABLE): $(OBJ)
    $(CPP) $(LDFLAGS) $^ -o $@