Make: Setting variable based on target

I want to set a variable depending on the assigned target. For instance:

if target == filename_a then
  VAR1 = YES
if target == filename_b then
  VAR2 = YES

Obviously, this is pseudo-code and not proper make-syntax.

What I really want to do is to include different make-files and include-directories dependent on target. Some targets share the same settings, and hence it is easier to maintain in one makefile.

An example of what it will be used for later:

ifeq ($(VAR1), YES)
  include foo.mk
endif
ifeq ($(VAR2), YES)
  include baz.mk
endif

Unfortunantly the following syntax cannot be used:

target : VAR1 = YES

Since this variable assignment is only 开发者_JAVA技巧valid through the process of actually building target, as I understand it.

The target environment is ClearMake 7 under Solaris, so please avoid any GNU Make specific solutions.

Thanks

Edit: As far as I can tell, make does not work in a way where the target is available during the processing step. Hence the feature asked for does most likely exist.

I'd be surprised if this can work, since as I understand it, Make processes include statements before it knows what targets it needs to make. But I know nothing about ClearMake and I'm not really an expert, so hopefully someone proves me wrong...