Simple makefile generation utility?

Does anyone know of a tool that generates a makefile by scanning 开发者_运维技巧a directory for source files?

It may be naive:

• no need to detect external dependencies
• use default compiler/linker settings

You can write a Makefile that does this for you:

SOURCES=$(shell find . -name "*.cpp")
OBJECTS=$(SOURCES:%.cpp=%.o)
TARGET=foo

.PHONY: all
all: $(TARGET)

$(TARGET): $(OBJECTS)
        $(LINK.cpp) $^ $(LOADLIBES) $(LDLIBS) -o $@

.PHONY: clean
clean:
        rm -f $(TARGET) $(OBJECTS)

Just place this in root directory of your source hierarchy and run make (you'll need GNU Make for this to work).

(Note that I'm not fluent in Makefileish so maybe this can be done easier.)

CMake does it and it even creates makefiles and Visual Studio projects. http://www.cmake.org/

All you need to do is creating a CMakeLists.txt file containing the follwing lines:

file(GLOB sources *.h *.c *.cxx *.cpp *.hxx)
add_executable(Foo ${sources})

Then go into a clean directory and type:

cmake /path/to/project/

That will create makefiles on that clean build directory.

This is what I would use for a simple project:

CC               = $(CXX)
CXXFLAGS        += -ansi -pedantic -W -Wall -Werror
CPPFLAGS        += -I<Dir Where Boost Lives>


SOURCES          = $(wildcard *.cpp)
OBJECTS          = $(patsubst %.cpp,%.o,$(SOURCES))

all:             myApp
myApp:           $(OBJECTS)

The only restriction is that if you are building an executable called myApp. Then one of the source files should be named myApp.cpp (which is where I put main).

There's a very old script called 'makedepend' that used to make very simple makefiles. I've since switched over to cmake for almost everything.

Here's the wiki article http://en.wikipedia.org/wiki/Makedepend, note the list of Alternatives at the bottom including depcomp in automake, and the -M flag in gcc.

EDIT: As someone pointed out to me in another question, gcc -MM *.cpp > Makefile produces a rather nice simple makefile. You only have to prepend your CPPFLAGS and a rule for constructing the entire binary... which will take the form:

CPPFLAGS=-Wall
LDFLAGS=-lm
all: binary_name
binary_name: foo.o bar.o baz.o biff.o

• no need to detect external dependencies
• use default compiler/linker settings

Why script then? Provided that all your project source files are *.cpp and in current directory:

all: $(notdir $(CURDIR))
$(notdir $(CURDIR)): $(subst .cpp,.o,$(wildcard *.cpp))
        $(LINK.cpp) $^ $(LOADLIBES) $(LDLIBS) -o $@

The Makefile would build the all the source files with default compiler/linker settings into an executable named after the name of the current directory.

Otherwise, I generally recommend people to try SCons instead of make where it is much simpler and intuitive. Added bonus that there is no need to code manually clean targets, source/header dependency checking is built-in, it is natively recursive and supports properly libraries.

As described in the linked discussion, HWUT is a tool that can generate pretty Makefiles, searching for dependencies and include files in directories that you tell it. On windows you need to install MinGW and Ctags. Under Linux gcc and ctags are most likely present. It is OpenSource and free to use.

Especially, when generating Unit Tests for some already existing modules of some larger project with bad cohesion, this feautures easily spares you hours or even days.