Dynamic targets in Makefiles

I'm trying to create a Makefile that has a target per src/ subfolder so that it creates a static lib.

I am currently trying this:

%.o: %.cpp
    $(CXX) $(CXXFLAGS) $(INCLUDE) -c -o $@ $<
lib%.a: $(patsubst %.cpp, %.o, $(wildcard src/%/*.cpp))
    $(AR) rcs $@ $^ 

But this doesn't work, the target matching works, but the dependency tracking doesn't.

If I just leave alone src/%/*.cpp that completes properly to t开发者_如何学运维he .cpp files in the proper dir, but the moment I try to use it inside string functions to convert the .cpp to .o the % does not work anymore.

This is tricky because as far as I know you can't use functions like patsubst in the prerequisite list. There is more than one way to do it; this is perhaps the least ugly. Store the path in a variable, then reinvoke make so that you can construct the prerequisite list outside the rule.

ifdef OBJPATH
LIBOBJECTS := $(patsubst %.cc,%.o,$(wildcard src/$(OBJPATH)/*.cc))
lib%.a: $(LIBOBJECTS)
    $(AR) rcs $@ $^
else
lib%.a: src/%/*.cc
    @$(MAKE) -s $@ OBJPATH=$*
endif