Makefile updated library dependency

I have a large makefile which builds several libraries, installs them, and then keeps on building objects which link against those installed libraries. My trouble is that I want to use "-lfoo -lbar" as g开发者_C百科++ flags to link against the two installed libraries, but the dependencies get messed up. If I change a header "42.h" which the library foo depends on, then of course make will rebuild and install it, but it does not appear to notice that my object "marvin" used "-lfoo" and marvin is left linked against the old version... :(

Thus far, I've been doing:

$(myObject): $(localSrc) /explicit/path/to/lib/libfoo.a
            $(CXX) $(CPPFLAGS) $(INCFLAGS) -o $@ $^ $(LINKFLAGS) $(LINKLIBS)

But I'm at a point where this is no longer a viable option. I need to simply add libraries "-lfoo -lbar" to the LINKFLAGS variable and have the linker figure things out?

In the mean time, I've aliased a few commands to explicitly blow away the object file(s) in question and then call make, but this is getting silly. I'm pressed for time, but if necessary I could post a small example perhaps Friday evening or Saturday morning.

Hence, I feel like I'm back in some bad version of windows dll hell. Is there something I can do to make the linker take notice of the version of the libraries that an object was built against and relink it if those libraries change??

Updated: So I hadn't had a chance to crash the suggestions until now. The drawback of what I'm doing is using static libraries. So I can't use ldd. So I rewrote my Makefile and found a way around this problem. If I get time, I'll post what I did.

How about this:

LIBS = foo bar blah # and so on

LINKFLAGS = $(addprefix -l,$(LIBS))

LIBPATHS = $(patsubst %,/explicit/path/to/lib/lib%.so, $(LIBS))

$(myObject): $(localSrc) $(LIBPATHS)
        $(CXX) $(CPPFLAGS) $(INCFLAGS) -o $@ $^ $(LINKFLAGS) $(LINKLIBS)

As far as I know, make in general isn't very good at automatically detecting dependencies like this. (It's not really make's job; make is a higher-level tool that's not aware of the specifics of the commands that it's spawning or what those commands do.)

Two options come to mind.

First, you could run ldd on $(myObject), save its list of libraries to a text file, then feed that back into your makefile as a list of dependencies. (This is similar to using -MD to save a list of header files to a text file then feeding that back into the makefile as additional rules for source file compilation, as Sam Miller suggested.)

Second, you could use a LINKLIBS variable as you've been using, and use GNU Make's functions to let the same variable work for both dependencies and command-line options. For example:

LINKLIBS := /explicit/path/to/lib/libfoo.so
$(myObject): $(localSrc) $(LINKLIBS)
        $(CXX) $(CPPFLAGS) $(INCFLAGS) -o $@ $^ $(LINKFLAGS) $(patsubst %,-l:%,$(LINKLIBS))

You might try the gcc dependency generation arguments like -MD, it's not clear to me if you are using them.